lc3564rm,rt-10lv/12lv/15lv sanyo electric co., ltd. semiconductor business headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan 60597ha(id) / 50995th(id) / d2293jn no. 4484?/10 ordering number: en 4484b cmos lsi 64k (8192 words 8 bits) sram overview the lc3564rm,rt are 8192-word 8bit, asynchronous, silicon gate, low-voltage cmos sram lsis.they oper- ate from a 2.0 to 3.6v supply, making them ideal for hand- held, battery-operated equipment. they are fully cmos devices employing 2-layer a1 wir- ing to realize high-speed access, low operating current consumption and very low standby current. they incorpo- rate control signal inputs; oe for high-speed memory access, and 2 chip enables ce1 and ce2 for power-down and device selection. they are ideal for systems requiring high speed, low power and battry backup or for easy mamory expansion. the very low standby current means that backup can also be achieved using a capacitor. features n supply voltage range: 2.0 to 3.6v 3v operation: 2.7 to 3.6v battery operation: 2.0 to 2.4v n high-speed access time 3v operation - lc3564rm,rt-10lv: 100ns (max) - lc3564rm,rt-12lv: 120ns (max) - lc3564rm,rt-15lv: 150ns (max) battery operation - lc3564rm,rt-10lv: 200ns (max) - lc3564rm,rt-12lv: 250ns (max) - lc3564rm,rt-15lv: 300ns (max) n very-low standby current 3v operation -ta 70 c: 1.0 m a -ta 85 c: 3.0 m a battery operation -ta 70 c: 0.85 m a -ta 85 c: 2.5 m a n operating temperature range: ?0 to +85 c n data retention supply voltage: 2.0 to 3.6v n input/output levels: cmos compatible (0.8vcc/0.2vcc) n 3 control inputs (oe , ce1 , ce2) n common-pin input/outputs, 3-state output n clock not needed (fully-static ram) n package sop 28-pin (450mil) plastic package: lc3564rm series tsop 28-pin (8 13.4mm) plastic package: lc3564rt series package dimensions unit: mm 3158 - sop28 unit: mm 3221 - tsop28 [lc3564rm] [lc3564rt]
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 pin assignment block diagram
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 pin functions truth table note: x = h or l speci?ations absolute maximum ratings at ta = 25 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condi- tions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. inout/output capacitance at ta = 25 c, f = 1 mhz note: measured samples only. number name function 1 nc no connection 2 to 10, 21, 23 to 25 a0 to a12 address inputs 27 we read/write control input 22 oe output enable input 20, 26 ce1 , ce2 chip enable inputs 11 to 13, 15 to 19 i/o1 to i/o8 data input/outputs 28, 14 v cc , gnd supply and ground pins mode ce1 ce2 oe we1 i/o supply current read cycle l h l h data output i cca write cycle l h x l data input i cca output disable l h h h high impedance i cca no selection h x x x high impedance i ccs x l x x high impedance i ccs parameter symbol conditions ratings unit maximum supply voltage v cc max 4.6 v input voltage range v in - 0.3 to v cc + 0.3 v input/output voltage range v i/o - 0.3 to v cc + 0.3 v operating temperature range t opr - 40 to +85 c storage temperature range t stg - 55 to +125 c parameter symbol conditions ratings unit min. typ. max. input/output pin capacitance c i/o v i/o = 0v - 6 10 pf input pin capacitance c i v i = 0v - 6 10 pf
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 3v operation dc recommended operating ranges at ta = ?0 to +85 c, v cc = 2.7 to 3.6v dc electrical characteristics at ta = ?0 to +85 c, v cc = 2.7 to 3.6v * when pulsewidth is less than 30 ns, the minimum value is -2.0v. *v cc = 3.0v, ta = 25 c parameter symbol ratings unit min. typ. max. supply voltage v cc 2.7 3.0 3.6 v input voltage v ih 0.8v cc -v cc + 0.3 v v il - 0.3 * - 0.2v cc v parameter symbol conditions ratings unit min. typ. * max. input leakage current i li v in = 0v to v cc - 1.0 - +1.0 m a i/o leakage current i lo v ce1 = v ih or v ce2 = v il or v oe = v ih or v we = v il , v i/o = 0v to v cc - 1.0 - +1.0 m a output high level voltage v oh i oh = - 2.0ma v cc - 0.4 - - v output low level voltage v ol i ol = 2.0ma - - 0.4 v operating supply current v cc 0.2v/0.2v input i cca1 v ce1 0.2v, v ce2 3 v cc ?0.2v, i i/o = 0ma, v in 0.2v or v in 3 v cc ?0.2v ta 70 c - 0.01 1.0 m a ta 85 c - - 3.0 m a cmos input i cca2 v ce1 = v il , v ce2 = v ih, i i/o = 0ma, v in = v ih or v il -- 4ma i cca3 v ce1 = v il , v ce2 = v ih, i i/o = 0ma, duty = 100% min. cycle - - 25 ma 200 ns cycle - - 15 ma 1 m s cycle - - 10 ma standby supply current v cc - 0.2v/0.2v input i ccs1 v ce2 0.2v or {v ce1 3 v cc - 0.2v, v ce2 3 v cc - 0.2v} ta 70 c - 0.01 1.0 m a ta 85 c - - 3.0 m a cmos input i ccs2 v ce2 = v il or v ce1 = v ih , v in = 0v to v cc -- 1ma
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 ac electrical characteristics at ta = ?0 to +85 c, v cc = 2.7 to 3.6v ac test conditions input pulse voltage level: 0.2v cc to 0.8 v cc input rise and fall times: 5 ns input/output timing level: v cc /2 output load: 30 pf (including jig capacitance) read cycle write cycle parameter symbol lc3564rm,rt unit -10lv -12lv -15lv min. max. min. max. min. max. read cycle time t rc 100 - 120 - 150 - ns address access time t aa - 100 - 120 - 150 ns ce1 access time t ca1 - 100 - 120 - 150 ns ce2 access time t ca2 - 100 - 120 - 150 ns oe access time t oa - 50 - 60 - 75 ns output hold time t oh 10 - 10 - 10 - ns ce1 output enable time t coe1 10 - 10 - 10 - ns ce2 output enable time t coe2 10 - 10 - 10 - ns oe output enable time t ooe 5- 5 - 5 - ns ce1 output disable time t cod1 - 35 - 40 - 50 ns ce2 output disable time t cod2 - 35 - 40 - 50 ns oe output disable time t ood - 25 - 30 - 40 ns parameter symbol lc3564rm,rt unit -10lv -12lv -15lv min. max. min. max. min. max. write cycle time t wc 100 - 120 - 150 - ns address setup time t as 0- 0 - 0 - ns write pulsewidth t wp 60 - 70 - 80 - ns ce1 setup time t cw1 70 - 80 - 90 - ns ce2 setup time t cw2 70 - 80 - 90 - ns write recovery time t wr 0- 0 - 0 - ns ce1 write recovery time t wr1 0- 0 - 0 - ns ce2 write recovery time t wr2 0- 0 - 0 - ns data setup time t ds 50 - 55 - 60 - ns data hold time t dh 0- 0 - 0 - ns ce1 data hold time t dh1 0- 0 - 0 - ns ce2 data hold time t dh2 0- 0 - 0 - ns we output enable time t woe 5- 5 - 5 - ns we output disable time t wod - 35 - 40 - 45 ns
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 battery operation dc recommended operating ranges at ta = ?0 to +85 c, v cc = 2.0 to 2.4v dc electrical characteristics at ta = ?0 to +85 c, v cc = 2.0 to 2.4v *v cc = 2.2v, ta = 25 c parameter symbol ratings unit min. typ. max. supply voltage v cc 2.0 2.2 2.4 v input voltage v ih 0.8v cc -v cc + 0.3 v v il ?.3 - 0.2v cc v parameter symbol conditions ratings unit min. typ. * max. input leakage current i li v in = 0v to v cc ?.0 - +1.0 m a i/o leakage current i lo v ce1 = v ih or v ce2 = v il or v oe = v ih or v we = v il , v i/o = 0v to v cc ?.0 - +1.0 m a output high level voltage v oh i oh = ?.5ma v cc ?0.2 - - v output low level voltage v ol i ol = 0.5ma - - 0.2 v operating supply current v cc 0.2v/0.2v input i cca1 v ce1 0.2v, v ce2 3 v cc ?0.2v, i i/o = 0ma, v in 0.2v or v in 3 v cc ?0.2v ta 70 c - 0.01 0.85 m a ta 85 c - - 2.5 m a cmos input i cca2 v ce1 = v il , v ce2 = v ih, i i/o = 0ma, v in = v ih or v il --2ma i cca3 v ce1 = v il , v ce2 = v ih, i i/o = 0ma, duty = 100% min. cycle - - 10 ma 1 m s cycle - - 5 ma standby supply current v cc ?0.2v/0.2v input i ccs1 v ce2 0.2v or {v ce1 3 v cc ?0.2v, v ce2 3 v cc ?0.2v} ta 70 c - 0.01 0.85 m a ta 85 c - - 2.5 m a cmos input i ccs2 v ce2 = v il or v ce1 = v ih , v in = 0v to v cc - - 800 ma
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 ac electrical characteristics at ta = ?0 to +85 c, v cc = 2.0 to 2.4v ac test conditions input pulse voltage level: 0.2v cc to 0.8 v cc input rise and fall times: 10 ns input/output timing level: v cc /2 output load: 30 pf (including jig capacitance) read cycle write cycle parameter symbol lc3564rm,rt unit -10lv -12lv -15lv min. max. min. max. min. max. read cycle time t rc 200 - 250 - 300 - ns address access time t aa - 200 - 250 - 300 ns ce1 access time t ca1 - 200 - 250 - 300 ns ce2 access time t ca2 - 200 - 250 - 300 ns oe access time t oa - 120 - 130 - 150 ns output hold time t oh 10 - 10 - 10 - ns ce1 output enable time t coe1 10 - 10 - 10 - ns ce2 output enable time t coe2 10 - 10 - 10 - ns oe output enable time t ooe 5- 5 - 5 - ns ce1 output disable time t cod1 - 70 - 80 - 100 ns ce2 output disable time t cod2 - 70 - 80 - 100 ns oe output disable time t ood - 50 - 60 - 80 ns parameter symbol lc3564rm,rt unit -10lv -12lv -15lv min. max. min. max. min. max. write cycle time t wc 200 - 250 - 300 - ns address setup time t as 0- 0 - 0 - ns write pulsewidth t wp 120 - 140 - 160 - ns ce1 setup time t cw1 140 - 160 - 180 - ns ce2 setup time t cw2 140 - 160 - 180 - ns write recovery time t wr 0- 0 - 0 - ns ce1 write recovery time t wr1 0- 0 - 0 - ns ce2 write recovery time t wr2 0- 0 - 0 - ns data setup time t ds 120 - 130 - 150 - ns data hold time t dh 0- 0 - 0 - ns ce1 data hold time t dh1 0- 0 - 0 - ns ce2 data hold time t dh2 0- 0 - 0 - ns we output enable time t woe 5- 5 - 5 - ns we output disable time t wod - 70 - 80 - 90 ns
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 timing chart read cycle: note 1 write cycle 1 (we write): note 6
lc3564rm,rt-10lv/12lv/15lv no. 4484?/10 write cycle 2 (ce1 write): note 6 write cycle 3 (ce2 write): note 6 note: 1. we should be held high level during the read cycle 2. do not apply external signals that are out-of-phase with d out 3. t wp is a period when ce1 and we are low and ce2 is high. it is measured from when we goes low level to when either ce1 and we go high or ce2 goes low, whichever occurs ?st. 4. t cw1 and t cw2 are periods when ce1 and we are low and ce2 is high. they are measured from when ce1 goes low and ce2 goes high, respectively, to when either ce1 and we go high or ce2 goes low, whichever occurs ?st. 5. the outputs d out1 to d out8 are in a high-impedance state when oe is high, ce1 is high, ce2 is low and we is low. 6. during the write cycle, oe is v ih or v il . 7. d out has the same phase as the write data.
lc3564rm,rt-10lv/12lv/15lv no. 4484?0/10 n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirec tly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its af?iates, subsidiaries and distributors and all their of?ers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses asso ciated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its af?iates, subsidiaries and distributors or any of their of?ers and employees, jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume pro duction. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringeme nts of intellectual property rights or other rights of third parties. this catalog provides information as of june, 1997. speci?ations and information herein are subject to change without notice. data retention characteristics at ta = ?0 to +85 c 3v operation note: t rc is the read cycle time. data retention waveform 1 (ce1 control) parameter symbol conditions ratings unit min. typ. max. data retention supply voltage v dr v ce1 3 v cc ?0.2v, v ce2 3 v cc ?0.2v or v ce2 0.2v 2.0 - 3.6 v chip enable setup time t cdr 0--ns chip enable hold time t r t rc --ns battery operation parameter symbol conditions ratings unit min. typ. max. data retention supply voltage v dr v ce1 3 v cc ?0.2v, v ce2 3 v cc ?0.2v or v ce2 0.2v 2.0 - 3.6 v data retention waveform 2 (ce2 control)
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